Test Time Minimization for Hybrid BIST of Systems-on-Chip
نویسندگان
چکیده
The main goal of this thesis was to develop an experimental environment for the test time minimization problem. It assumes Hybrid BIST architecture and targets System-on-Chip designs. The thesis is based on methodology developed during the work and demonstrates the feasibility of the proposed methodology together with experimental results. First two sections of this thesis explore the actuality of the problem and provide background information. Further, the proposed methodology is discussed for the case
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